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Sheet目录3871

72页 73页 74页 75页 [76页]77页 78页 79页 80页

dsPIC30F1010/202X

DS70178C-page 166

Preliminary

2006 Microchip Technology Inc.

REGISTER 15-2:

U1STA: UART1 STATUS AND CONTROL REGISTER

R/W-0

U-0

R/W-0

UTXISEL1

UTXINV(1)

UTXISEL0

—

UTXBRK

UTXEN

UTXBF

TRMT

bit 15

bit 8

R/W-0

URXISEL1

URXISEL0

ADDEN

RIDLE

PERR

FERR

OERR

URXDA

bit 7

bit 0

Legend: U = Unimplemented bit, read as ‘0’

R = Readable bit

W = Writable bit

HS =Hardware Set

HC = Hardware Cleared

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 15, 13

UTXISEL1:UTXISEL0: Transmission Interrupt Mode Selection bits

=Reserved; do not use

=Interrupt when a character is transferred to the Transmit Shift Register and as a result, the

transmit buffer becomes empty

=Interrupt when the last character is shifted out of the Transmit Shift Register; all transmit

operations are completed

=Interrupt when a character is transferred to the Transmit Shift Register (this implies there is at

least one character open in the transmit buffer)

bit 14

UTXINV: IrDA Encoder Transmit Polarity Inversion bit(1)

= IrDA encoded U1TX idle state is ‘1’

= IrDA encoded U1TX idle state is ‘0’

Note 1: Value of bit only affects the transmit properties of the module when the IrDA encoder is

enabled (IREN = 1).

bit 12

Unimplemented: Read as ‘0’

bit 11

UTXBRK: Transmit Break bit

= Send Sync Break on next transmission – Start bit, followed by twelve ‘0’ bits, followed by Stop bit;

cleared by hardware upon completion

= Sync Break transmission disabled or completed

bit 10

UTXEN: Transmit Enable bit

= Transmit enabled, U1TX pin controlled by UART1

= Transmit disabled, any pending transmission is aborted and buffer is reset. U1TX pin controlled by

PORT.

bit 9

UTXBF: Transmit Buffer Full Status bit (Read-Only)

= Transmit buffer is full

= Transmit buffer is not full, at least one more character can be written

bit 8

TRMT: Transmit Shift Register Empty bit (Read-Only)

= Transmit Shift Register is empty and transmit buffer is empty (the last transmission has

completed)

= Transmit Shift Register is not empty, a transmission is in progress or queued

bit 7-6

URXISEL1:URXISEL0: Receive Interrupt Mode Selection bits

=Interrupt is set on RSR transfer, making the receive buffer full (i.e., has 4 data characters)

=Interrupt is set on RSR transfer, making the receive buffer 3/4 full (i.e., has 3 data characters)

=Interrupt is set when any character is received and transferred from the RSR to the receive buffer.

Receive buffer has one or more characters.

bit 5

ADDEN: Address Character Detect bit (bit 8 of received data = 1)

= Address Detect mode enabled. If 9-bit mode is not selected, this does not take effect.

0 = Address Detect mode disabled

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